The present invention relates generally to array circuit designs, and more specifically to improving margins of the array circuit.
Complimentary metal-oxide semiconductor field-effect transistor (CMOS) technology is becoming increasingly miniaturized. This leads to complexities in designing static random access memory (SRAM). SRAM contains one or more arrays, wherein each array is a data structure composed of a collection of elements (e.g., values or variables) identified by at least one array index or key. During a write operation, the SRAM cell must flip in order to write new data in the cell. During a read operation, the SRAM cell must not flip in order to prevent data loss. There is only a certain area on the SRAM cell where reliable read and write operations are possible. Degradative processes, such as bias temperature instability (BTI), weaken n-type metal-oxide semiconductor (NMOS) field-effect transistors (FETs) and p-type metal-oxide semiconductor (PMOS) FETs. The SRAM cell stores bits (i.e., a basic unit of information in computing) as data storage elements using bi-stable latching circuity. The bi-stable latching circuitry, which contain NMOS FETs and PMOS FETs, stores state information on each bit. The binary nature of these bits is represented in terms of two states—“zero” or “one.” In other words, each bit is in the “zero” state or the “one” state.